5,887 Verification Engineer jobs in the United Kingdom

Verification Engineer

Cambridge, Eastern Riverlane

Posted 13 days ago

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Job Description

Permanent

Cambridge, UK | Full-time or Part-time | Permanent | Hybrid

Salary: £55,000 to £68,000 DOE

We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.

About us

Riverlane’s mission is to make quantum computing useful, sooner. From advances in material science to complex chemistry simulation for drug design and discovery, quantum computers will help solve some of the world’s most important challenges. Riverlane is building the quantum error correction stack, Deltaflow, to make this happen. It’s a complex problem that requires a range of skills, talent and passion.

We recently raised $75M in Series C funding to accelerate our cutting-edge R&D in quantum error correction (QEC), and are partnering with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.

About the role

You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified, trusted and performant solution. With full visibility of the entire stack, you will own everything verification related. As a Senior Verification Engineer at Riverlane, you will:

  • Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level.
  • Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests.
  • Maintain the design verification environment, keeping track of regression, coverage metrics and bugs.

You do not need a background in quantum computing! You will learn this along the way.

Requirements

What we need

  • Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.
  • A proactive and collaborative person who actively shares feedback and can independently define the scope of work.
  • Proven experience of testbench design with verification frameworks like UVM/OVM.
  • Knowledge of SystemVerilog assertion (SVA).
  • Exposure to different programming languages, such as C, C++ and Python.

Even better if

  • You have formal verification experience.

Benefits

What can you expect from us

  • A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme  
  • Equity, so that our team can share in the long-term success of Riverlane
  • 28 days annual leave, plus bank holidays and enhanced family leave
  • A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities
  • A learning environment that encourages individual, team and company growth and learning, including an annual training and conference budget for each staff member
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Verification Engineer

Bristol, South West Codasip

Posted 131 days ago

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Job Description

Permanent

**Please note this role is only open to candidates currently located in and with working rights to the UK**

Welcome to Codasip

We believe Codasip is the most innovative processor solutions company. We take pride in designing and developing cutting-edge, high-performance, and energy-efficient RISC-V CPU cores from scratch to power some of the most exciting applications - think high performance supercomputers and next-generation embedded systems. By also providing our own automated proprietary tools to fully customize these cores, we give our customers a unique competitive advantage by empowering their system-on-chip developers to build the most innovative products.

What you’ll do

We’re looking for passionate Verification Engineers to help bring our vision to life. You’ll be a key part of verifying complex, state-of-the-art CPUs, including advanced out-of-order processors. Taking ownership of portions of the design, you’ll apply a range of verification methodologies and play a vital role in setting high standards for a brand-new platform.

This is a unique chance to work on clean-sheet designs that push technological boundaries and make a real impact. Join us in Cambridge or Bristol and be part of a team redefining what’s possible in CPU design.

You will:

  • Verify RISC-V processors and extensions
  • Develop verification solutions (e.g. test benches and test bench components, stimulus generation, formal environments)
  • Collaborate with other engineers in a team responsible for the delivery of all verification activities related to a component or subsystem from start to finish
  • Define, estimate, prioritise and track your own work, with support from others
  • Help define verification strategies for block and sub-systems, identifying and utilising the right tools
  • Review technical specifications, providing feedback from a verification perspective
  • Run simulations, hunt bugs and complete root cause analysis of complex issues
  • Help track and report verification metrics
  • Help craft automated verification flows

Requirements

What we need

  • Commercial experience with functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, test generation, coverage collection, gate level simulation etc…)
  • Knowledge of verifying CPU architectures or other IP
  • Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go
  • Analytical thinking and team collaboration skills

What we’d love you to have

  • Past verification ownership of a design block
  • User knowledge of Linux to enable automation of common tasks
  • Knowledge of versioning tools (Git, SVN)
  • Knowledge of RISC-V Architecture
  • Good knowledge of computer systems and architecture

Benefits

What's in it for you?

Join a flexible, open and supportive team full of curious, self-motivated and driven engineers who are keen to explore new ways of doing things, you'll get to work on ultra-modern, cutting-edge products and technology.

As a Codasipper, you will have the freedom to explore original solutions and experiment with new techniques in your role. We believe in cross-departmental awareness and encourage collaboration, allowing you to add value through diversity in your daily work.

So, come aboard and let's architect a future of innovation together! We can't wait to see what you'll achieve at Codasip.

Some useful Links on Codasip:

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Design Verification Engineer

Cambridgeshire, Eastern IC Resources

Posted 6 days ago

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DV Engineer

Quantum StartUp


I am seeking a Senior Verification Engineer to join a rapidly growing HW Team in Cambridge. You will get the opportunity to work on cutting edge technology and in the area of quantum computing. No prior experience in quantum computing? No problem. You'll learn as you go while working alongside world-class engineers in a truly cross-disciplinary environment.

About the role

As a Senior Verification Engineer , you’ll take full ownership of functional verification across their hardware systems. You’ll collaborate with a talented team of hardware designers and embedded software engineers to deliver trusted, high-performance solutions—verified from the ground up. With full visibility of the stack, you’ll define verification strategies, implement robust test environments, and ensure confidence in every design you deliver.

What you’ll do

  • Work closely with hardware designers and system architects to define and own verification plans based on design specifications
  • Develop scalable SystemVerilog testbenches , including checkers, coverage groups, and reference models
  • Design and run self-checking, directed, and randomized tests
  • Maintain the verification environment, including tracking regressions, bugs, and coverage metrics
  • Drive quality and performance across block-level and system-level designs

Core skills

  • Strong commercial experience in functional verification , with ownership of verification strategy and planning
  • Expertise in testbench design using frameworks like UVM or OVM
  • Proficiency with SystemVerilog assertions (SVA)
  • Familiarity with multiple programming languages (e.g., C, C++, Python )

Visa sponsorship will be provided for candidates who require. Please note, you must already be living and working in the United Kingdom. You must also be prepared to work onsite 3 days per week in Cambridge.

For more information, please contact Rachel Mason at IC Resources.

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Hardware Verification Engineer

Baya Systems

Posted 6 days ago

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Job Title: Senior Hardware Verification Engineer

Location: England, United Kingdom (Remote anywhere inside the country)

About the Role: We are seeking a seasoned Design Verification designer with a strong background in building testbenches and writing test sequences for complex IPs. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities:

  • Collaborate with design and architecture teams to create test plans for highly configurable IPs meant to provide interconnectivity between components across an SOC, chiplet or multi chiplet systems
  • Write UVM/SystemVerilog code to implement the test plan, checkers and scoreboards
  • Collaborate with software teams to define and implement configurable testbenches
  • Work with design and DV engineers to implement the test plan, debug failures, close coverage, etc.

Qualifications:

  • BS/MS in Electrical Engineering, Computer Engineering or Computer Science
  • 8+ years and current hands-on experience in block-level/IP-level/SOC-level verification
  • Proficiency in Verilog, SystemVerilog
  • Familiarity with industry-standard EDA tools for simulation and debug
  • Deep experience with UVM-based testbenches
  • Experience with modern programming languages like Python
  • Knowledge of ARM AMBA protocols such as AXI, APB, and AHB
  • Understanding of ARM CHI protocol is a plus
  • Experience on working with IPs for caches, cache coherency, memory subsystems, interconnects and NOCs
  • Experience with formal verification techniques, emulation platforms is a plus
  • Excellent problem-solving skills and attention to detail
  • Strong communication and collaboration skills


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Design Verification Engineer

Sheffield, Yorkshire and the Humber IC Resources

Posted 6 days ago

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Design Verification Engineer

Manchester/Sheffield/Leeds

UK REMOTE can be considered


This is a fantastic opportunity to join a start-up who are just over 2 years old, as they make technological breakthroughs in security with a product line built on CHERI technology and RISC‑V cores.


They have strong funding behind them and a leadership team made up of experts in processor design and formal methods as well as a CEO who brings over 30 years of semiconductor experience from world renown companies and start-ups. With huge growth plans across the Silicon Design team this is a fantastic time to join the business!

I am looking for a talented Verification Engineer to join a rapidly growing stealth mode start-up. The successful candidate will play a key role in the verification of hardware, specifically focusing on security features utilizing CHERI technology.


Responsibilities

  • Collaborates with the design team to understand and define verification requirements for security features
  • Develops and maintains verification plans, testbenches, and test scenarios using UVM methodology
  • Executes test plans and verifies the correctness of hardware security features
  • Works closely with the cross-functional teams to ensure the implementation meets design specifications and security requirements
  • Identifies and debugs issues found during verification and works to resolve them in a timely manner


Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
  • Strong understanding of hardware verification methodologies and tools
  • Experience with UVM (Universal Verification Methodology) for FPGA/ASIC verification
  • Familiarity with security features and protocols, such as CHERI, is a plus
  • Excellent communication skills and the ability to work effectively in a collaborative, multidisciplinary team
  • Knowledge of UK working rights


Day-to-day

  • Collaborates with the design team to understand and define verification requirements
  • Develops and maintains verification plans, testbenches, and test scenarios
  • Executes test plans and verifies the correctness of hardware security features
  • Identifies and debugs issues found during verification and works to resolve them in a timely manner
  • Communicates progress and findings to the cross-functional teams


North of UK or UK Remote: You must be currently living and working in the UK and able to do so without restrictions.

You must have UK working rights to be considered for the role.

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Design Verification Engineer

Oxford, South East IC Resources

Posted 6 days ago

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Verification Engineer


An excellent opportunity has arisen to join a global leader in advanced semiconductor technologies. This role offers the chance to work on cutting-edge 5nm designs, supporting the latest PCIe interfaces, protocols, and NAND flash solutions.

While part of a large international organisation, the UK site operates with the feel of a fast-moving startup but with the stability and backing of a major company. The team builds on over a decade of SSD design expertise, applying a proven methodology that combines RTL design with high-speed microcode engines—delivering flexibility to meet new requirements while minimising the risk of re-spins.

The ASIC team is involved in every stage of the development flow—from requirements capture and architecture through to development, verification, tape-out, and post-silicon support. This provides excellent opportunities both for engineers looking to broaden their skills across the full lifecycle and for those who want to specialise in areas such as UVM-based verification.

As a Verification Engineer, you will join an industry-leading SoC development team tackling complex design challenges including high-speed interfaces, high-performance accelerators, and multi-CPU architectures. Team responsibilities span SoC architecture, RTL design, verification, synthesis, FPGA prototyping, and validation.

Why Oxfordshire?

Oxfordshire offers a fantastic quality of life, combining a world-renowned university city with beautiful countryside. With excellent schools, cultural attractions, and easy access to London and Heathrow, it’s an ideal location for both professionals and families.

Essential qualifications and skills

  • Bachelor’s or Master’s degree in Electronic Engineering (or related field)
  • Experience in digital ASIC design and verification, including:
  • Defining functional requirements for verification environments & metrics
  • SystemVerilog UVM testbenches
  • Formal proof verification
  • Understanding of C test cases and C code
  • Scripting languages (e.g. Python, Perl, TCL)

Desirable skills

  • Experience with formal verification tools (JasperGold, VC Formal)
  • Familiarity with C/C++ development
  • Prior SSD experience with storage interfaces such as SAS or PCIe (NVMe preferred)

What’s on offer

  • Competitive base salary
  • Hybrid working model
  • Generous company pension scheme
  • Private health insurance
  • Visa sponsorship and relocation support for experienced engineers

For more information or a confidential discussion, please contact Rachel Mason at IC Resources.

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Design Verification Engineer

IC Resources

Posted 6 days ago

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ASIC Verification Engineer

Bristol or Cambridge

3 days onsite work

Leading compensation and benefits package


This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future of humanity. A chance to work on products that have set the standard in made-for-AI compute hardware and software. A chance to be part of the AI revolution!


Whilst this is an individual contributor role you can expect a clear career path and progression into technical leadership and managerial roles if that is something you seek.


I am looking for Verification Engineers to join a world class Silicon Engineering team, joining a company who bring large and ongoing investment from one of the world’s leading backers of innovative AI companies! SW Verification experience with Python, C/C++ is welcome alongside the traditional UVM based Verification.


Responsibilities and Duties

  • Verification activities within the verification team
  • Ensuring good communication between sites
  • Verification planning, specification and closure of functional coverage
  • Providing feedback to architects
  • Test generation and failure diagnosis/triage
  • Contributing to shared verification infrastructure


Candidate Profile

Essential:

  • Verification experience in relevant industry
  • Proven leadership and planning skills
  • Ability to work across teams and programming languages to find root causes of deep and complex issues
  • Experience of the verification process applied in CPU and/or ASIC environments
  • System Verilog, Python, C++, Linux
  • UVM
  • SVA
  • LLVM, GCC
  • SGE or other DRMS
  • XML and XPath/XSLT


Benefits

In addition to a competitive salary, you can expect flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection.


For more info please contact Rachel Mason at IC Resources

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Design Verification Engineer

IC Resources

Posted 6 days ago

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This is a fantastic opportunity to join an established UK design team in Bristol and play a key role in the growth and success of a global leader in wireless technology for IoT . You’ll be working on chips from first principles through to final silicon , with the chance to see your work powering real-world products used by world-leading brands across gaming, wireless PC peripherals, sports and fitness, mobile accessories, consumer electronics, healthcare, and automation .

As an ASIC Verification Engineer , you’ll focus on the verification of WiFi SoCs , with a strong emphasis on low-power design . You’ll develop advanced UVM-based testbenches, collaborate with cross-functional teams, and help drive verification strategies for next-generation ultra-low-power wireless devices.

Responsibilities

  • Develop and implement UVM-based testbenches for ASIC verification
  • Verify low-power features and optimise for energy efficiency
  • Contribute to the verification of complex SoC designs
  • Debug and analyse hardware design issues
  • Collaborate with design and architecture teams to ensure verification quality

Qualifications

  • Bachelor’s or Master’s in Electrical Engineering (or related field)
  • Strong experience in ASIC verification and digital hardware design
  • Skilled in SystemVerilog / UVM testbench development
  • Knowledge of low-power verification techniques
  • Familiarity with C for testbench development is a plus
  • Experience in WiFi/wireless SoC development is desirable
  • Excellent communication and problem-solving skills

Day-to-day

  • Collaborate with design teams to understand intent and requirements
  • Build, maintain, and run UVM-based testbenches
  • Perform simulations and debug issues
  • Develop and maintain verification test plans and documentation
  • Participate in design and code reviews

What’s on offer

  • Base salary: £60,000 – £75,000 DOE
  • RSUs + bonus scheme
  • Visa sponsorship and relocation support available

If you’re passionate about ASIC verification and excited to contribute to world-class WiFi SoCs , this role offers an excellent opportunity to grow your career in a supportive and innovative team.

Contact Rachel at IC Resources to apply.

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Design Verification Engineer

Edinburgh, Scotland IC Resources

Posted 6 days ago

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Design Verification Engineers — Next-Generation AI ASICs

Cambridge or Edinburgh


An innovative fabless semiconductor start-up is developing cutting-edge AI accelerator chips designed to deliver an order-of-magnitude performance improvement while dramatically reducing power consumption.


I am seeking experienced Verification Engineers to ensure the functional correctness and robustness of complex AI accelerator designs. You will play a key role in developing advanced verification environments and driving coverage closure to achieve first-silicon success.


Key Responsibilities

  • Collaborate with design and architecture teams to define and implement verification strategies for AI accelerator blocks and SoC subsystems.
  • Build scalable SystemVerilog/UVM testbenches, including test plans, monitors, checkers, scoreboards, and constrained-random stimulus.
  • Perform coverage-driven and assertion-based verification, analyse coverage reports, and close functional and code coverage gaps.
  • Debug complex hardware–software interactions, reproduce silicon issues in simulation, and work closely with RTL, architecture, and software engineers to resolve them.
  • Develop verification frameworks that scale across unit-level simulation, emulation, and post-silicon validation, incorporating high-level models and test generators.


Qualifications

  • Proven experience in digital IC design verification, preferably with exposure to CPU, GPU, NPU, or AI accelerator IP.
  • Strong skills in SystemVerilog, UVM, and scripting languages such as Python, C++, Perl, or TCL.
  • Solid understanding of computer architecture, memory hierarchies, and standard interconnects (e.g., AMBA/AXI, NoC).
  • Familiarity with formal verification, assertion-based methodologies, and low-power verification techniques is a plus.
  • Ability to thrive in a fast-paced start-up environment, collaborating effectively across hardware and software teams.


Desirable Experience

  • 5+ years of verification experience in high-performance or AI-oriented ASIC development.
  • Background in AI chip design verification or accelerator verification methodologies.


This is a superb opportunity to shape next-generation AI hardware from the ground up, working with a passionate team that values innovation, technical excellence, and collaboration.


You will join as one of the first Chip Engineers within an organisation with huge funding.

On offer is a top salary! You must have UK working rights.

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Design Verification Engineer

Edinburgh, Scotland IC Resources

Posted 6 days ago

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Design Verification Engineer

Edinburgh


I have an exciting opportunity for a talented Verification Engineer to join an Edinburgh or Newbury based HW Team. As a Verification Engineer you will participate in all aspects of digital verification for complete mixed signal IC developments, work on complex verification systems and contribute towards improvements in verification methodology within the business.

This is a real chance for you to get heavily involved in cutting-edge projects working in a global organisation.

Responsibilities:

  • Definition of IC verification plan linking product requirements through to detailed testcases
  • Leading teams of verification engineers to deliver thoroughly verified ICs
  • Create reliable and reusable testbench for complex subsystems and ICs
  • Participate in verification specialist groups and contribute to the digital verification methodology discussions
  • Supporting, and where necessary coaching, the verification team to follow, and improve, defined methodology practices
  • Hands-on project design/verification involvement

Required Skills and Qualifications

  • BEng / BSc / MEng / MSc Degree or equivalent in Electronics/Computer Science or other related discipline.
  • Metric driven verification – verification planning, requirements extraction – directed and constrained random verification – functional and code coverage analysis
  • SystemVerilog – SVA (SystemVerilog Assertions)
  • Testbench design with verification frameworks like UVM/OVM, e, VMM
  • Debugging skills – RTL – Testbench, OOP – Gate level (including SDF)
  • Scripting experience with Ruby, sh/csh, TCL, Make, Perl
  • Power aware verification (using CPF/UPF)

This position is based in Edinburgh.

This is a hybrid remote position and will follow a 2+ day in-office work schedule, with in-office days based on business needs and team preference. You must be based within commutable distance of Edinburgh or Newbury or willing to relocate

In return, on offer you will a great range of benefits including personal and professional development, a uniquely flat culture and much, much more!

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