396 Verification Engineer jobs in the United Kingdom

Verification Engineer - (phone number removed) - £27.30/hr umbrella rate (Inside IR35)

Are you ready to accelerate your career in the automotive engineering industry? This is an incredible opportunity to join a forward-thinking company as a Verification Engineer. Be part of a team that thrives on innovation, precision, and collaboration, working on cutting-edge projects that push the boundaries of engineering excellence. If you're passionate about mechatronic systems, vehicle dynamics, and HIL testing, this company is looking for someone like you to drive their projects forward.

What You Will Do:  

- Develop and execute test cases within the Steering System HIL environment, ensuring top-level performance.

- Implement existing vehicle test procedures within the Steering HIL framework to support system validation.

- Operate and maintain the Steering System HIL rig, ensuring smooth functionality.

- Analyse test results using advanced methods and metrics to deliver actionable insights.

- Collaborate with internal teams to address test requests and generate detailed reports.

- Correlate virtual models with Steering System HIL and vehicle data to optimise system performance.

What You Will Bring:

- Extensive experience in HIL testing with tools such as DSPACE or XPACK4.

- Strong knowledge of vehicle dynamics principles and mechatronic systems validation.

- Proficiency in vehicle simulation software like Matlab/Simulink or IPG Carmaker.

- Programming expertise and problem-solving skills, including familiarity with methodologies like Six Sigma.

- Knowledge of machine learning techniques and AGILE methodology.

This company is committed to delivering excellence in engineering and innovation. As a Verification Engineer, you'll play a pivotal role in ensuring their systems meet the highest standards of quality and performance. Your contributions will directly impact the development of advanced steering systems, making a difference in the automotive industry.

Location:  This role is based in Gaydon, a hub for automotive innovation and technology. 

Interested?:  If you're ready to take on this exciting challenge as a Verification Engineer, don't wait! Apply now and join a team where your skills and expertise will be valued and nurtured. Let's drive the future of engineering together.

Your CV will be forwarded to Jonathan Lee Recruitment, a leading engineering and manufacturing recruitment consultancy established in 1978. The services advertised by Jonathan Lee Recruitment are those of an Employment Agency.
In order for your CV to be processed effectively, please ensure your name, email address, phone number and location (post code OR town OR county, as a minimum) are included.

Cambridge, UK | Full-time or Part-time | Permanent | Hybrid

Salary: £55,000 to £68,000 DOE

We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.

Riverlane’s mission is to make quantum computing useful, sooner. From advances in material science to complex chemistry simulation for drug design and discovery, quantum computers will help solve some of the world’s most important challenges. Riverlane is building the quantum error correction stack, Deltaflow, to make this happen. It’s a complex problem that requires a range of skills, talent and passion.

We recently raised $75M in Series C funding to accelerate our cutting-edge R&D in quantum error correction (QEC), and are partnering with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.

You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified, trusted and performant solution. With full visibility of the entire stack, you will own everything verification related. As a Senior Verification Engineer at Riverlane, you will:

• Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level.
• Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests.
• Maintain the design verification environment, keeping track of regression, coverage metrics and bugs.

You do not need a background in quantum computing! You will learn this along the way.

Requirements

What we need

• Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.
• A proactive and collaborative person who actively shares feedback and can independently define the scope of work.
• Proven experience of testbench design with verification frameworks like UVM/OVM.
• Knowledge of SystemVerilog assertion (SVA).
• Exposure to different programming languages, such as C, C++ and Python.

Even better if

• You have formal verification experience.

Benefits

What can you expect from us

• A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme  
• Equity, so that our team can share in the long-term success of Riverlane
• 28 days annual leave, plus bank holidays and enhanced family leave
• A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities
• A learning environment that encourages individual, team and company growth and learning, including an annual training and conference budget for each staff member

**Please note this role is only open to candidates currently located in and with working rights to the UK**

Welcome to Codasip

We believe Codasip is the most innovative processor solutions company. We take pride in designing and developing cutting-edge, high-performance, and energy-efficient RISC-V CPU cores from scratch to power some of the most exciting applications - think high performance supercomputers and next-generation embedded systems. By also providing our own automated proprietary tools to fully customize these cores, we give our customers a unique competitive advantage by empowering their system-on-chip developers to build the most innovative products.

What you’ll do

We’re looking for passionate Verification Engineers to help bring our vision to life. You’ll be a key part of verifying complex, state-of-the-art CPUs, including advanced out-of-order processors. Taking ownership of portions of the design, you’ll apply a range of verification methodologies and play a vital role in setting high standards for a brand-new platform.

This is a unique chance to work on clean-sheet designs that push technological boundaries and make a real impact. Join us in Cambridge or Bristol and be part of a team redefining what’s possible in CPU design.

You will:

• Verify RISC-V processors and extensions
• Develop verification solutions (e.g. test benches and test bench components, stimulus generation, formal environments)
• Collaborate with other engineers in a team responsible for the delivery of all verification activities related to a component or subsystem from start to finish
• Define, estimate, prioritise and track your own work, with support from others
• Help define verification strategies for block and sub-systems, identifying and utilising the right tools
• Review technical specifications, providing feedback from a verification perspective
• Run simulations, hunt bugs and complete root cause analysis of complex issues
• Help track and report verification metrics
• Help craft automated verification flows

Requirements

What we need

• Commercial experience with functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, test generation, coverage collection, gate level simulation etc…)
• Knowledge of verifying CPU architectures or other IP
• Fluency and the ability to write clear and concise code in languages like SystemVerilog, Python, C++, Rust, or Go
• Analytical thinking and team collaboration skills

What we’d love you to have

• Past verification ownership of a design block
• User knowledge of Linux to enable automation of common tasks
• Knowledge of versioning tools (Git, SVN)
• Knowledge of RISC-V Architecture
• Good knowledge of computer systems and architecture

Benefits

What's in it for you?

Join a flexible, open and supportive team full of curious, self-motivated and driven engineers who are keen to explore new ways of doing things, you'll get to work on ultra-modern, cutting-edge products and technology.

As a Codasipper, you will have the freedom to explore original solutions and experiment with new techniques in your role. We believe in cross-departmental awareness and encourage collaboration, allowing you to add value through diversity in your daily work.

So, come aboard and let's architect a future of innovation together! We can't wait to see what you'll achieve at Codasip.

Some useful Links on Codasip:

• Codasip RISC V Processor Solutions
• Design for differentiation: architecture licenses in RISC‑V
• Scaling is Failing - Dr. Ron Black, CEO, Codasip

My client is a globally recognised semiconductor company developing a new product family based on RISC-V architecture, marking a significant evolution in their technology roadmap.

They’re seeking skilled verification engineers to support the increased demand for functional verification across a variety of complex IPs. This growth reflects both long-term investment in R&D and a strategic shift in architecture, making it an exciting time to join.

Principal Verification Engineer

Responsibilities:

• Develop and maintain SystemVerilog UVM testbenches for complex IPs.
• Lead the creation of new UVM verification components and contribute to testbench architecture
• Debug test failures and define functional coverage models to ensure sign-off quality.
• Work closely with designers and contribute to verification strategy during design and concept phases.
• Improve verification efficiency and ensure compliance with functional safety and quality standards.

Requirements:

• Minimum 5 years of IP-level verification experience using SystemVerilog UVM.
• Strong understanding of UVM methodology, SVAs, and verification metrics.
• Ability to interpret complex design specifications and create robust verification environments.
• Proficiency in industry-standard EDA tools and scripting languages.
• Excellent communication skills and a methodical, detail-focused approach.

Apply to learn more!

Product Verification Engineer
Barnsley, Permanent

If youre the kind of person who loves solving problems, digging into the details, and making sure things work exactly as they should, this is your chance to help shape high-quality, reliable products from the ground up. Youll be stepping into a growing team where your work has a direct impact on the performance, safety, and product reliability. This .

Cambridge, UK | Full-time or Part-time | Permanent | Hybrid

Salary: £68,000 to £80,000 DOE

We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.

Riverlane’s mission is to make quantum computing useful, sooner. From advances in material science to complex chemistry simulation for drug design and discovery, quantum computers will help solve some of the world’s most important challenges. Riverlane is building the quantum error correction stack, Deltaflow, to make this happen. It’s a complex problem that requires a range of skills, talent and passion.

We recently raised $75M in Series C funding to accelerate our cutting-edge R&D in quantum error correction (QEC), and are partnering with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.

You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified, trusted and performant solution. With full visibility of the entire stack, you will own everything verification related. As a Senior Verification Engineer at Riverlane, you will:

• Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level.
• Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests.
• Maintain the design verification environment, keeping track of regression, coverage metrics and bugs.

You do not need a background in quantum computing! You will learn this along the way.

Requirements

What we need

• Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.
• A proactive and collaborative person who actively shares feedback and can independently define the scope of work.
• Proven experience of testbench design with verification frameworks like UVM/OVM.
• Knowledge of SystemVerilog assertion (SVA).
• Exposure to different programming languages, such as C, C++ and Python.

Even better if

• You have formal verification experience.

Benefits

What can you expect from us

• A comprehensive benefits package that includes an annual bonus plan, private medical insurance, life insurance, and a contributory pension scheme  
• Equity, so that our team can share in the long-term success of Riverlane
• 28 days annual leave, plus bank holidays and enhanced family leave
• A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics and maths) and over 20 different nationalities
• A learning environment that encourages individual, team and company growth and learning, including an annual training and conference budget for each staff member

Cambridge, UK | Full-time or Part-time | Permanent | Hybrid

Salary: £65,000 to £80,000 DOE  

We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter. 

About us 

Riverlane’s mission is to make quantum computing useful, sooner. From advances in material science to complex chemistry simulation for drug design and discovery, quantum computers will help solve some of the world’s most important challenges. Riverlane is building the quantum error correction stack, Deltaflow, to make this happen. It’s a complex problem that requires a range of skills, talent and passion.  

We recently raised $75M in Series C funding to accelerate our cutting-edge R&D in quantum error correction (QEC), and are partnering with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast.  

About the role 

You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified, trusted and performant solution. With full visibility of the entire stack, you will own everything verification related.  As a Senior Verification Engineer at Riverlane, you will:  

• Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level. 

• Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests. 

• Maintain the design verification environment, keeping track of regression, coverage metrics and bugs. 

You do not need a background in quantum computing!  You will learn this along the way. 

What you will do 

You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified, trusted and performant solution. With full visibility of the entire stack, you will own everything verification related.  As a Senior Verification Engineer at Riverlane, you will:  

• Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level. 

• Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests. 

• Maintain the design verification environment, keeping track of regression, coverage metrics and bugs. 

You do not need a background in quantum computing!  You will learn this along the way. 

Requirements

What we need 

• Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy. 
• A proactive and collaborative person who actively shares feedback and who can independently define the scope of work. 
• Proven experience of testbench design with verification frameworks like UVM/OVM. 
• Knowledge of SystemVerilog assertion (SVA). 
• Exposure to different programming languages, such as C, C++ and Python 

Even better if 

• You have formal verification experience  

Benefits

What you can expect from us 

• A comprehensive benefits package, including annual bonus scheme, private medical insurance, life insurance, a contributory pension scheme (and much more) 

• Equity so that our team can share in the long-term success of Riverlane 

• 28 days annual leave (plus bank holidays) and enhanced family leave 

• A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics, maths and many more) and over 20 different nationalities 

• A learning environment that encourages individual, team and company growth and learning, including an annual training and conference budget 

 
How to apply 

Please upload a CV and cover letter by clicking 'Apply'. Your cover letter should explain why you are applying for the job and what skills and experience you can bring to the role. 

We review CVs as we receive them and interview as soon as we have applications that look like a good match (usually within one week). We do not use closing dates. So, please apply as soon as possible to avoid missing out on this role. We advertised this role on 4th April 2025 . If you have any queries, please contact  . 

Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity. 

Studies have shown that women tend to apply to jobs if they meet all or almost all of the requirements whereas men apply even if they meet only some of the requirements. If that sounds like you then please apply – we are happy to review your application and let you know if we think you might be a good fit. 

If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help. 

• Degree or equivalent qualification in Systems engineering or similar
  
• Systems design/ systems engineering experience in software-based equipment
  
• Hands-on experience of SysML, Rhapsody and DOORS tools would be desirable, but training will be provided where needed.
  
• Experience in the Defence / Aerospace or safety regulated environment would be advantageous
  

• Bonus : Up to 2,500 (based on performance).
  
• Pension : Up to 14% total contribution.
  
• Parental Leave : Enhanced parental, maternity, and shared parental leave.
  
• Flexi Leave : Up to 15 additional days.
  
• Facilities : On-site perks like subsidised meals and free parking.
  
• Training and Development : Excellent opportunities for career progression and skill development
  

• The company are a multi-national group, being No 1 in Europe for what they do! With a number of awards and recognitions, with great career progression and opportunities across the business!
  
• It's no wonder, they have been among the winners of the annual Glassdoor Employees' Choice Awards, 2022, and most recently receiving three accreditation gold standard awards with Investors in People!
  
• "Interesting work. Good work-life balance. Employees made to feel valued." Software Engineer, 5 Dec 2022. *Glassdoor review.
  
• "Promotes and believes in a good work/life balance interesting work on most programmes Encourages internal mobility. Offers good development/training opportunities" Principal Systems Engineer, 19 Dec 2022. *Glassdoor review.
  
• True advocates of ED&I as an Equal Opportunity Employer! With over 10 Networking groups and communities across the business advocating Equity, Diversity and Inclusion.
  
• Enhanced parental leave: Offers up to 26 weeks for maternity, adoption and shared parental leave. Enhancements are available for paternity leave, neonatal leave and fertility testing and treatments.